The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices.
For semiconductor power devices, super-junction (also referred to as vertical charge-balance) designs offer several advantages. For example, super-junction devices demonstrate reduced on-resistance and reduced conduction losses relative to conventionally designed unipolar power devices. SiC SJ drift layers can be applied to a variety of power devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), diodes, as well as other devices that may be useful for medium-voltage (e.g., 2 kV-10 kV) and high-voltage (e.g., greater than or equal to 10 kV) power conversion related applications.
In silicon (Si) super-junction (SJ) devices, design features such as active regions of vertical pillars may be formed/implemented either by implanting or by diffusing dopants of p-type into a Si device layer of n-type. The vertical pillars of these Si-SJ devices extend through the thickness (e.g., tens of micrometers) of the Si device layer, which can be achieved using one or both of existing Si implantation and diffusion methods. Edge termination regions in Si-SJ devices, may be implemented by ion implantation processes and diffusing dopants similar to the active cells, or by using filled trenches of silicon oxide (SiO2), silicon or poly-silicon (Si). Edge termination regions generally prevent electric field crowding near the edges of the active region during reverse bias.
However, in silicon carbide (SiC), there are significant differences. For example, dopants have significantly lower diffusion coefficients than in Si. As a result, when a device design feature, such as an active region with a vertical charge-balance pillar, is to be fabricated by implanting dopants into an epitaxial layer using implantation energies typical of Si processing, the dopants are unable to penetrate as deeply into a SiC layer. For example, common high-volume ion implantation systems for Si device fabrication enable dopant implantation energies up to about 380 keV. Such implantation energies only enable dopant implantation to a maximum depth between about 0.5 μm and about 1 μm into a SiC layer. Additionally, due to technological constrains and incomplete activation of dopants, effective doping concentrations provided by both implantation doping and in-situ epitaxial growth doping while fabricating SiC devices can vary up to about 20% from the designed doping concentrations. Thus, achieving desired both n-type and p-type doping control is difficult when fabricating SiC-based super-junction power devices.
In addition, significantly higher electric fields present in SiC-SJ devices under reverse bias, prevent some of conventional Si edge termination techniques from being utilized in SiC-SJ devices. As such, it is desirable to provide effective edge termination designs for SiC-SJ devices to ensure reliable and robust device operation during reverse bias.